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| ht32f52231/HT32F52241 ht32f52331/ht32f52341 datasheet 32-bit arm ? cortex?-m0+ microcontroller, up to 64 kb flash and 8 kb sram with 1 msps adc, usart, uart, spi, i 2 c, mctm, gptm, sctm, bftm, sci, crc, rtc, wdt, and usb2.0 fs revision: v1.51 date: april 11, 2017
rev. 1.51 2 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 table of contents table of contents 1 general description ........... ..................................................................................... 6 2 features ................................................................................................................... 7 core ....................................................................................................................................... 7 on-chip memory .................................................................................................................... 7 flash memory controller C fmc ............ ................................................................................ 7 reset control unit C rstcu ................................................................................................. 8 clock control unit C ckcu ............ ........................................................................................ 8 power management C pwrcu ............................................................................................. 8 external interrupt/event controller C exti ............................................................................ 9 analog to digital converter C adc ........................................................................................ 9 i/o ports C gpio .................................................................................................................... 9 motor control timer C mctm .............................................................................................. 10 pwm generation and capture timers C gptm .................................................................. 10 single channel generation and capture timers C sctm ................................................... 11 basic function timer C bftm ............................................................................................. 11 watchdog timer C wdt ....................................................................................................... 11 real time clock C rtc ....................................................................................................... 12 inter-integrated circuit C i 2 c ................................................................................................ 12 serial peripheral interface C spi ......................................................................................... 12 universal synchronous asynchronous receiver transmitter C usart .............................. 13 universal asynchronous receiver transmitter C uart ...................................................... 13 smart card interface C sci (ht32f52331/52341 only) ...................................................... 14 cyclic redundancy check C crc ....................................................................................... 14 universal serial bus device controller C usb (ht32f52331/52341 only) ......................... 15 debug support ..................................................................................................................... 15 package and operation temperature .................................................................................. 15 3 overview ................................................................................................................ 16 device information ............................................................................................................... 16 block diagram ..................................................................................................................... 17 memory map ........................................................................................................................ 18 clock structure ........... ......................................................................................................... 21 4 pin assignment ..................................................................................................... 22 rev. 1.51 3 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 table of contents table of contents 5 electrical characteristics ..................................................................................... 32 absolute maximum ratings ................................................................................................. 32 recommended dc operating conditions ........................................................................... 32 on-chip ldo voltage regulator characteristics ................................................................. 32 power consumption ............................................................................................................ 33 reset and supply monitor characteristics ........................................................................... 35 external clock characteristics ............................................................................................. 36 internal clock characteristics .............................................................................................. 37 pll characteristics .............................................................................................................. 37 memory characteristics ....................................................................................................... 37 i/o port characteristics ........................................................................................................ 38 adc characteristics ........... ................................................................................................. 39 sctm/gptm/mctm characteristics ............ ....................................................................... 40 i 2 c characteristics ............................................................................................................... 41 spi characteristics ........... ................................................................................................... 42 usb characteristics ............................................................................................................. 44 6 package information ............................................................................................ 45 24-pin ssop (150mil) outline dimensions ............ .............................................................. 46 28-pin ssop (150mil) outline dimensions ............ .............................................................. 47 saw type 33-pin (4mm4mm) qfn outline dimensions ................................................... 48 48-pin lqfp (7mm7mm) outline dimensions ................................................................... 49 rev. 1.51 4 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 list of tables list of tables table 1. features and peripheral list ...... ................................................................................................ 16 table 2. register map ............................................................................................................................. 19 table 3. ht32f52231/52241 series pin assignment for 24/28ssop, 33qfn, 48lqfp package ....... ... 28 table 4. ht32f52331/52341 series pin assignment for 33qfn, 48lqfp package .............................. 29 table 5. ht32f52231/52241 pin description ...... .................................................................................... 30 table 6. ht32f52331/52341 pin description ...... .................................................................................... 31 table 7. absolute maximum ratings ........................................................................................................ 32 table 8. recommended dc operating conditions .................................................................................. 32 table 9. ldo characteristics ...... ............................................................................................................. 32 table 10. ht32f52231/52241 power consumption characteristics ....................................................... 33 table 11. ht32f52331/52341 power consumption characteristics ....................................................... 34 table 12. v dd power reset characteristics ............................................................................................. 35 table 13. lvd/bod characteristics ......................................................................................................... 35 table 14. high speed external clock (hse) characteristics ................................................................... 36 table 15. low speed external clock (lse) characteristics .................................................................... 36 table 16. high speed internal clock (hsi) characteristics ..................................................................... 37 table 17. low speed internal clock (lsi) characteristics ....................................................................... 37 table 18. pll characteristics .................................................................................................................. 37 table 19. flash memory characteristics .................................................................................................. 37 table 20. i/o port characteristics ............................................................................................................ 38 table 21. adc characteristics ................................................................................................................. 39 table 22. sctm/gptm/mctm characteristics ...... ................................................................................. 40 table 23. i 2 c characteristics .................................................................................................................... 41 table 24. spi characteristics ................................................................................................................... 42 table 25. usb dc electrical characteristics ........................................................................................... 44 table 26. usb ac electrical characteristics ............................................................................................ 44 rev. 1.51 5 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 list of tables list of figures list of figures figure 1. block diagram .......................................................................................................................... 17 figure 2. memory map ............................................................................................................................. 18 figure 3. clock structure ......................................................................................................................... 21 figure 4. ht32f52231/52241 24-pin ssop pin assignment .................................................................. 22 figure 5. ht32f52231/52241 28-pin ssop pin assignment .................................................................. 23 figure 6. ht32f52231/52241 33-pin qfn pin assignment .................................................................... 24 figure 7. ht32f52231/52241 48-pin lqfp pin assignment ................................................................... 25 figure 8. ht32f52331/52341 33-pin qfn pin assignment .................................................................... 26 figure 9. ht32f52331/52341 48-pin lqfp pin assignment ................................................................... 27 figure 10. adc sampling network model ............................................................................................... 40 figure 11. i 2 c timing diagrams ............................................................................................................... 41 figure 12. spi timing diagrams C spi master mode ...... ........................................................................ 42 figure 13. spi timing diagrams C spi slave mode with cpha=1 ....... ................................................... 43 figure 14. usb signal rise time and fall time and cross-point voltage (vcrs) defnition ....... .......... 44 rev. 1.51 6 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 general description 1 general description the holtek ht32f522x1/523x1 devices are high performance , low power consumption 32-bit microcontroller s based around a n arm ? cor tex?-m 0+ processor core. the cortex?-m 0+ is a next - generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer , and including advanced debug support. the devices operate at a frequency of up to 40mhz for ht32f52231/52241 and 48 mhz for ht32f52331/52341 with a flash accelerator to obtain maximum efficiency. it provides up to 64kb of embedded flash memory for code/data storage and 8 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, u s art, uart, s pi , mctm, gptm, sctm, crc-16/32, rtc, wdt, sci, usb2.0 fs, sw-dp (serial wire debug port) , etc. , are also implemented in th e device series . several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the device s are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitor s, alarm systems, consumer products, handheld equipment, data logging applications , motor control and so on. rev. 1.51 7 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 general description features 2 features core 32-bit arm ? cortex?-m0+ processor core up to 40mhz operati ng frequency for ht32f52231/52241 or 48mhz for ht32f52331/52341 0.93 dmips/mhz (dhrystone v2.1) single-cycle multiplication integrated nested vectored interrupt controller (nvic) 24-bit systick timer the cortex-m0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized, low-power processor. the processor is based on the armv6-m architecture and supports thumb ? instruction sets; single-cycle i/o port; hardware multiplier and low latency interrupt respond time. on-chip memory up to 64 kb on-chip flash memory for instruction/data and options storage 8 kb on-chip sram supports multiple boot modes the arm ? cortex?-m0+ processor accesses and debug accesses share the single external interface to external ahb peripheral. the processor accesses take priority over debug accesses. the maximum address range of the cortex?-m0+ is 4 gb since it has a 32-bit bus address width. additionally, a pre-defined memory map is provided by the cortex?-m0+ processor to reduce the software complexity of repeated implementation by different device vendors. however, some regions are used by the arm ? cortex?-m0+ system peripherals. refer to the arm ? cortex?-m0+ technical reference manual for more information. figure 2 shows the memory map of the ht32f52231/52241 and ht32f52331/52341 series of devices, including code, sram, peripheral, and other pre-defned regions. flash memory controller C fmc flash accelerator for maximum effciency 32-bit word programming with in system programming interface (isp) and in application programming (iap) flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory word program/page erase functions are also provided. rev. 1.51 8 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features reset control unit C rstcu supply supervisor: power on reset / power down reset C por/pdr brown-out detector C bod programmable low voltage detector C lvd the reset control unit , rstcu , has three kinds of reset, a power on reset, a system reset and an apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit C ckcu external 4 to 16mhz crystal oscillator external 32,768 hz crystal oscillator internal 8mhz rc oscillator trimmed to 2 % accuracy at 3.3v operating voltage and 25c operating temperature internal 32 khz rc oscillator integrated system clock pll independent clock divider and gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers, apb clock divider and gating circuitry. the ahb, apb and cortex tm -m0+ clocks are derived from the system clock (ck_ sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. power management C pwrcu single v dd power supply: 2.0v to 3.6v integrated 1.5v ldo regulator for cpu core, peripherals and memories power supply v dd power supply for rtc. two power domains: v dd , 1.5 v four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conficting demands of cpu operating time, speed and power consumption. rev. 1.51 9 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features features external interrupt/event controller C exti up to 16 exti lines with confgurable trigger source and type all gpio pins can be selected as exti trigger source source trigger type includes high level, low level, negative edge, positive edge, or both edge individual interrupt enable, wakeup enable and status bits for each exti line software interrupt trigger mode for each exti line integrated deglitch flter for short pulse blocking the external interrupt/event controller, exti, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. each exti line can also be masked independently. analog to digital converter C adc 12-bit sar adc engine up to 1 msps conversion rate up to 12 external analog input channels a 12-bit multi-channel adc is integrated in the device. there are multiplexed channels, which include 12 external analog signal channels and 2 internal channels which can be measured. if the input voltage is required to remain within a specifc threshold window, an analog watchdog function will monitor and detect the se signal s . an interrupt will then be generated to inform the device that the input voltage is not within the pre set threshold level s. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. i/o ports C gpio up to 40 gpios port a, b, c are mapped as 16 external interrupts C exti almost all i/o pins have a confgurable output driving current. there are up to 40 general purpose i/o pins, gpio, named from pa0 ~ pa15 to pc0 ~ pc7 for the implementation of logic input/output functions. each of the gpio ports has a series of related control and confguration registers to maximize fexibility and to meet the requirements of a wide range of applications. the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by configuring the corresponding registers regardless of the input or output pins. the external interrupts on the gpio pins of the device have related control and confguration registers in the external interrupt control unit , exti. rev. 1.51 10 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features motor control timer C mctm one 16-bit up, down, up/down auto-reload counter 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 input capture function compare match output pwm waveform generation with edge-aligned and center-aligned counting modes single pulse mode output complementary outputs with programmable dead-time insertion supports 3-phase motor control and hall sensor interface break input to force the timers output signals into a reset or fxed condition the motor control timer consists of a single 16-bit up/down counter, four 16-bit ccrs (capture/ compare register s ), single one 16-bit counter-reload register (crr), single 8-bit repetition counter and several control/status registers. it can be used for a variety of purposes including measuring the pulse width s of input signal s or generating output waveforms such as compare match output s , pwm output s or complementary pwm output s with dead-time insertion. th e mctm is capable of offering full functional support for motor control, hall sensor interfac ing and brake input. pwm generation and capture timers C gptm one 16-bit up, down, up/down auto-reload counter 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 input capture function compare match output pwm waveform generation with edge-aligned and center-aligned counting modes single pulse mode output encoder interface controller with two inputs using quadrature decoder the general purpose timer consists of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement , input signal pulse width measurement , output waveform generation such as single pulse generation , or pwm output generation . the gptm supports an encoder interface using a decoder with two inputs. rev. 1.51 11 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features features single channel generation and capture timers C sctm one 16-bit up and auto-reload counter one channel for each timer 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 input capture function compare match output pwm waveform generation with edge-aligned single pulse mode output the single-channel timer consists of one 16-bit up-counter, one 16-bit capture/compare register (ccr), one 16-bit counter-reload register (crr) and several control/status registers. it can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or pwm output. basic function timer C bftm one 32-bit compare/match count-up counter - no i/o control features one shot mode - counting stops after a match condition repetitive mode - restart counter after a match condition the basic function timer is a simple count- up 32-bit counter designed to measure time interval s and generate a one shot or repetitive interrupt s . the bftm operates in two functional modes, repetitive or one shot mode. in the repetitive mode the bftm restarts the counter when a compare match event occurs. the bftm also supports a o ne shot mode which forces the counter to stop counting when a compare match event occurs. watchdog timer C wdt 12-bit down counter with 3-bit prescaler reset event for the system programmable watchdog timer window function register write protection function the watchdog timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. it includes a 12-bit count- down counter, a prescaler, a wdt delta value register, wdt operation control circuitry and a wdt protection mechanism. if the software does not reload the counter value before a watchdog timer underfow occurs, a reset will be generated when the counter underflows. in addition, a reset is also generated if the software reloads the counter when the counter value is greater than the wdt delta value. this means the counter must be reloaded within a limited timing window using a specifc method. the watchdog timer counter can be stopped while the processor is in the debug mode. there is a register write protect function which can be enabled to prevent it from changing the watchdog timer confguration unexpectedly. rev. 1.51 12 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features real time clock C rtc 24-bit up-counter with a programmable prescaler alarm function interrupt and wake-up event the real time clock, rtc, includes an apb interface, a 24-bit count- up counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are located in the backup domain except for the apb interface. the apb interface is located in the v dd15 power domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd15 power domain is powered off, that is when the device enters the power- down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode. inter-integrated circuit C i 2 c supports both master and slave modes with a frequency of up to 1mhz provide an arbitration function and clock synchronization supports 7-bit and 10-bit addressing mode s and general call addressing supports slave multi-addressing mode with maskable address the i 2 c is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: (1) 100khz in the standard mode, (2) 400khz in the fast mode and (3) 1mhz in the fast plus mode . the scl period generation register is used to setup different kinds of duty cycle implementation s for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c also has an arbitration detect function and clock synchronization to prevent situation s where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi supports both master and slave mode frequency of up to (f pclk /2)mhz for the master mode and (f pclk /3)mhz for the slave mode fifo depth: 8 levels multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and output lines miso and mosi, the clock line, sck, and the slave select line, sel. one spi device acts as a master device which controls the data fow using the sel and sck signals to indicate the start of data communication and the data sampling rate. to receive a data byte, the streamed data bits are latched on a specifc clock edge and stored in the data register or in the rx fifo. data transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications. rev. 1.51 13 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features features universal synchronous asynchronous receiver transmitter C usart supports both asynchronous and clocked synchronous serial communication modes asynchronous operating baud rate up to (f pclk /16)mhz and synchronous operating rate up to (f pclk /8)mhz full duplex communication fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation bit order: lsb-frst or msb-frst transfer error detection: parity, overrun, and frame error auto hardware fow control mode C rts, cts irda sir encoder and decoder rs485 mode with output enable control fifo depth: 89 bits for both receiver and transmitter the universal synchronous asynchronous receiver transceiver, usart, provides a fexible full duplex data exchange using synchronous or asynchronous data transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the usart module includes a transmitter fifo, (tx_fifo) and receiver fifo (rx_fifo). the s oftware can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. universal asynchronous receiver transmitter C uart asynchronous serial communication operating baud-rate up to f pclk /16mhz full duplex communication fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation bit order: lsb-frst or msb-frst transfer error detection: parity, overrun, and frame error the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports line status interrupt. the s oftware can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. rev. 1.51 14 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features smart card interface C sci (ht32f52331/52341 only) supports iso 7816-3 standard character mode single transmit buffer and single receive buffer 11-bit etu (elementary time unit) counter 9-bit guard time counter 24-bit general purpose waiting time counter parity generation and checking automatic character retry on parity error detection in transmission and reception modes the smart card interface is compatible with the iso 7816-3 standard. this interface includes card insertion/removal detection, sci data transfer control logic and data buffers, internal timer counters and corresponding control logic circuits to perform all the necessary smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for sci transfer status. cyclic redundancy check C crc support crc16 polynomial: 0x8005, x 16 +x 15 +x 2 +1 support ccitt crc16 polynomial: 0x1021, x 16 +x 12 +x 5 +1 support ieee-802.3 crc32 polynomial: 0x04c11db7, x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 supports 1s complement, byte reverse & bit reverse operation on data and checksum supports byte, half-word & word data size programmable crc initial seed value crc computation executed in 1 ahb clock cycle for 8-bit data and 4 ahb clock cycles for 32-bit data supports pdma to complete a crc computation of a block of memory the crc calculation unit is an error detection technique test algorithm which is used to verify data transmission or storage data correctness. a crc calculation takes a data stream or a block of data as its input and generates a 16- or 32-bit output remainder. ordinarily, a data stream is suffxed by a crc code and used as a checksum when being sent or stored. therefore, the received or restored data stream is calculated by the same generator polynomial as described above. if the new crc code result does not match the one calculated earlier, then this means that the data stream contains a data error. rev. 1.51 15 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 features features universal serial bus device controller C usb (ht32f52331/52341 only) complies with usb 2.0 full-speed (12 mbps) specifcation on-chip usb full-speed transceiver 1 control endpoint (ep0) for control transfer 3 single-buffered endpoints for bulk and interrupt transfer 4 double-buffered endpoints for bulk, interrupt and isochronous transfer 1,024 bytes ep-sram used as the endpoint data buffers the usb device controller is compliant with the usb 2.0 full-speed specifcation. there is one control endpoint known as endpoint 0 and seven configurable endpoints. a 1024-byte sram is used as the endpoint buffer. each endpoint buffer size is programmable using corresponding registers, which provides maximum fexibility for various applications. the integrated usb full- speed transceiver helps to minimize the overall system complexity and cost. the usb functional block also contains the resume and suspend feature to meet the requirements of low-power consumption. debug support serial wire debug port C sw-dp 4 comparators for hardware breakpoint or code / literal patch 2 comparators for hardware watchpoints package and operation temperature 24/28-pin ssop, 33-pin qfn, 48-pin lqfp for ht32f52231/52241 33-pin qfn, 48-pin lqfp package for ht32f52331/52341 operation temperature range: -40c to +85c rev. 1.51 16 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview 3 overview device information table 1. features and peripheral list peripherals ht32f52231 HT32F52241 ht32f52331 ht32f52341 main flash (kb) 32 63 32 63 option bytes flash (kb) 1 1 1 1 sram (kb) 4 8 4 8 timers mctm 1 gptm 1 sctm 4 bftm 2 rtc 1 wdt 1 communication usb 1 spi 2 usart 1 uart 2 i 2 c 2 sci (iso7816-3) 1 crc-16/32 1 exti 16 12-bit adc number of channels 1 12 channels gpio up to 40 up to 38 cpu frequency up to 40mhz up to 48mhz operating voltage 2.0 v ~ 3.6 v operating temperature -40 c ~ +85 c package 24/28-pin ssop 33-pin qfn, 48-pin lqfp 33-pin qfn, 48-pin lqfp rev. 1.51 17 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview overview block diagram sw-dp apb ahb peripherals flash memory cortex tm -m0+ processor system nvic sram controller fmc control registers ckcu/rstcu control registers interrupt request usart afio exti ch3 ~ ch0 boot clock and reset control power control bus matrix af af af af powered by v dd15 swclk swdio sda scl af power supply: bus: control signal: alternate function: af powered by v dd15 mosi, miso sck, sel af flash memory interface tx, rx rts/txe cts/sck x32kin x32kout af lsi 32 khz lse 32,768 hz v dd v ss rtc pwrcu nrst rtcout wakeup af af powered by v dda v dda v ssa adc_in0 ... adc_in11 af i2c0 ~ 1 adc 12-bit sar adc mctm bftm0 ~ 1 ahb to apb bridge wdt gpio pa ~ pb[15:0]; pc[7:0] af tx, rx crc -16/32 ch0 ~ch2 ch0n ~ ch2n ch3, brk af io port uart0 uart0 ~ 1 spi1 ~ 0 spi1 ~ 0 powered by v dd v ss v dd por /pdr bod lvd xtalin xtalout hsi 8 mhz hse 4 ~ 16 mhz af ldo 1.5 v gptm cldo cap. powered by v dd sctm0 ~ 3 sctm0 ~ sctm3 af pll usb device af dp dm usb control/data registers sram sci clk, dio det af ht32f52331/41 only ht32f52331/41 only figure 1. block diagram rev. 1.51 18 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview memory map sci note reserved usb sram note usb note reserved reserved gpio a c reserved reserved reserved bftm1 bftm0 gptm rtc & pwrcu reserved reserved reserved reserved reserved reserved reserved reserved 0x4002_2000 uart1 reserved up to 64 kb on-chip flash 0x0000_0000 reserved 0x0001_0000 boot loader 0x1f00_0000 reserved 0x1f00_0800 option byte alias 0x1ff0_0000 up to 64 kb 2 kb 1 kb reserved 0x1ff0_0400 code sram peripheral up to 8 kb on-chip sram 0x2000_0000 reserved 0x2000_2000 8 kb apb peripherals 0x4000_0000 ahb peripherals 0x4008_0000 0x4010_0000 private peripheral bus 0xe000_0000 reserved 0xe010_0000 0xffff_ffff 512 kb 512 kb usart 0x4000_0000 uart0 0x4000_1000 spi0 spi1 0x4000_4000 i2c1 0x4000_5000 i2c0 adc reserved 0x4001_0000 exti 0x4002_3000 0x4004_5000 afio 0x4002_4000 mctm wdt 0x4004_2000 reserved 0x4003_6000 0x4004_8000 0x4002_c000 0x4006_9000 0x4002_d000 0x4006_b000 0x4006_a000 0x4004_a000 0x4006_e000 0x4003_4000 apb fmc 0x4008_0000 reserved 0x4008_2000 ckcu/rstcu 0x4008_8000 crc 0x4008_a000 0x400f_ffff ahb 0x4000_2000 0x4004_4000 0x4002_5000 0x4004_1000 0x4008_c000 0x400b_0000 0x400b_6000 0x4001_1000 0x4004_9000 0x4006_8000 0x4006_f000 0x4007_6000 0x4007_7000 0x4007_8000 sctm0 sctm2 0x4003_5000 sctm1 sctm3 0x4007_4000 0x4007_5000 reserved 0x400a_8000 0x400a_a000 0x400a_c000 0x4004_3000 note: ht32f52331/ht32f52341 only figure 2. memory map rev. 1.51 19 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview overview table 2. register map start address end address peripheral bus 0x4000_0000 0x4000_0fff usart0 apb 0x4000_1000 0x4000_1fff uart0 0x4000_2000 0x4000_3fff reserved 0x4000_4000 0x4000_4fff spi0 0x4000_5000 0x4001_9fff reserved 0x4001_0000 0x4001_0fff adc 0x4001_1000 0x4002_1fff reserved 0x4002_2000 0x4002_2fff afio 0x4002_3000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff exti 0x4002_5000 0x4002_bfff reserved 0x4002_c000 0x4002_cfff mctm 0x4002_d000 0x4003_3fff reserved 0x4003_4000 0x4003_4fff sctm0 0x4003_5000 0x4003_5fff sctm2 0x4003_6000 0x4004_0fff reserved 0x4004_1000 0x4004_1fff uart1 0x4004_2000 0x4004_2fff reserved 0x4004_3000 0x4004_3fff sci note 0x4004_4000 0x4004_4fff spi1 0x4004_5000 0x4004_7fff reserved 0x4004_8000 0x4004_8fff i2c0 0x4004_9000 0x4004_9fff i2c1 0x4004_a000 0x4006_7fff reserved 0x4006_8000 0x4006_8fff wdt 0x4006_9000 0x4006_9fff reserved 0x4006_a000 0x4006_afff rtc/pwrcu 0x4006_b000 0x4006_dfff reserved 0x4006_e000 0x4006_efff gptm 0x4006_f000 0x4007_3fff reserved 0x4007_4000 0x4007_4fff sctm1 0x4007_5000 0x4007_5fff sctm3 0x4007_6000 0x4007_6fff bftm0 0x4007_7000 0x4007_7fff bftm1 0x4007_8000 0x4007_ffff reserved rev. 1.51 20 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview start address end address peripheral bus 0x4008_0000 0x4008_1fff fmc ahb 0x4008_2000 0x4008_7fff reserved 0x4008_8000 0x4008_9fff ckcu/rstcu 0x4008_a000 0x4008_bfff crc 0x4008_c000 0x400a_7fff reserved 0x400a_8000 0x400a_bfff usb note 0x400a_c000 0x400a_ffff reserved 0x400b_0000 0x400b_1fff gpioa 0x400b_2000 0x400b_3fff gpiob 0x400b_4000 0x400b_5fff gpioc 0x400b_6000 0x400f_ffff reserved note: ht32f52331/ht32f52341 only. rev. 1.51 21 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 overview overview clock structure 4-16 mhz hse xtal 8 mhz hsi rc 32 khz lsi rc legend: hse = high speed external clock hsi = high speed internal clock lse = low speed external clock lsi = low speed internal clock 32.768 khz lse osc wdtsrc pllsrc ahb prescaler 1,2,4,8,16,32 fclk ( free running clock) stclk (to systick) ck_adc ip ck_wdt wdten ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[2:0] hseen hsien lseen (note1) lsien (note1) f ck_sys,max = 40 mhz for ht32f52231/52241 f ck_sys,max = 48 mhz for ht32f52331/52241 ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk (afio, adc, spix, usart, uartx, i2cx, mctm, gptm, sctmx, bftmx, exti, sci, wdt, rtc) pll clock monitor pllen ck_lse ck_pll adcen f ck_pll,max = 48 mhz ck_lsi hclks ( to sram) hclkf ( to flash) cm0pen fmcen cm0pen sramen 1 0 rtcsrc (note1) ck_rtc rtcen (note1) 1 0 1 0 ck_ahb 000 001 010 011 100 101 110 ck_sys sw[2:0] 8 ck_usb f ck_usb = 48 mhz usben hclkc ( to cortex tm -m0+) cm0pen (control by hw) prescaler 1 ~ 32 ck_ref divider 2 ckrefpre hclkbm ( to bus matrix) cm0pen bmen hclkapb ( to apb bridge) cm0pen apben ck_crc ( to crc) crcen peripherals clock prescaler 1,2,4,8 adc prescaler 1,2,3,4,8,... 00 01 10 11 pclk pclk/2 pclk/4 pclk/8 spien scien ck_gpio ( to gpio port) gpioden gpioaen ckrefen hsi auto trimming controller ck_lse usb ref pulse 00x 011 010 111 110 ht32f52331/52341 only figure 3. clock structure rev. 1.51 22 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment 4 pin assignment 1 2 3 4 5 6 7 8 9 pb7 pb8 vdda pa0 pa1 pa2 pa3 pa4 pa5 cldo pb4 pb3 pb2 pb1 pb0 pa9_boot xtalout xtalin af0 (default) 33v 33v 33v 33v 33v 33v ht32f52231/HT32F52241 24 ssop-a 10 af0 (default) 33v swclk swdio pa12 pa13 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 23 22 21 20 19 18 17 16 15 24 ap 11 vdd vss 12 p15 p33 p33 rtcout nrst 33v 33v 14 13 33v 33v p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad pb12 pb13 pb14 figure 4. ht32f52231/52241 24-pin ssop pin assignment rev. 1.51 23 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment pin assignment 1 2 3 4 5 6 7 8 9 10 11 pb7 pb8 vdda pa0 pa1 pa2 pa3 pa4 pa5 pa7 cldo pb4 pb3 pb2 pb1 pb0 pa15 pa9_boot xtalout xtalin af0 (default) 33v 33v 33v 33v 33v 33v ht32f52231/HT32F52241 28 ssop-a 12 af0 (default) 33v pa6 33v swclk swdio pa12 pa13 af1 pa14 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 27 26 25 24 23 22 21 20 19 18 17 28 ap 13 vdd vss 14 33v p15 p33 p33 rtcout nrst 33v 33v 16 15 33v 33v p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad pb12 pb13 pb14 figure 5. ht32f52231/52241 28-pin ssop pin assignment rev. 1.51 24 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment vssa pb5 vdda pb8 pb7 pb4 pb2 pb3 32 31 30 29 28 27 26 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 pb1 pb0 pa15 pa14 pa9_ boot xtalin af0 (default) af0 (default) af0 (default) vdd vss nrst x32kin x32kout rtcout p33 vdd 33v vdd 33v vdd 33v vdd 33v p15 33v ap ap ht32f52231/HT32F52241 33 qfn-a 25 cldo af0 (default) p33 33v 33v 33v 33v swclk swdio pa12 pa13 pb10 pb11 pb12 pb13 af1 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 17 xtalout pb14 33v 3.3 v digital & analog io pad p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital i/o pad vdd vdd domain pad 33 vss 1 2 3 4 5 6 7 8 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 33v 33v 33v 33v 33v 33v 33v 33v figure 6. ht32f52231/52241 33-pin qfn pin assignment rev. 1.51 25 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment pin assignment vssa pb6 vdda pb8 pb7 pc3 pc2 pc1 pb5 pb4 pb2 pb3 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 35 34 33 32 31 30 29 28 27 26 25 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc4 pc6 pc7 vss_2 vdd_2 pb1 pb0 pa15 pa14 pa10 pa9_ boot pa8 xtalin af0 (default) af0 (default) af0 (default) vdd_1 vss_1 nrst pb9 x32kin x32kout rtcout pc0 xtalout pb15 p33 vdd 33v vdd 33v vdd 33v vdd 33v vdd 33v p15 33v 33v 33v 33v 33v 33v 33v ap ap ht32f52231/HT32F52241 48 lqfp-a 37 12 24 36 cldo af0 (default) 33v pc5 p33 33v 33v p33 p33 33v 33v 33v swclk swdio pa12 pa13 pb10 pb11 pb12 pb13 pb14 af1 af1 pa11 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad vdd vdd domain pad 33v 33v 33v 33v figure 7. ht32f52231/52241 48-pin lqfp pin assignment rev. 1.51 26 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment vssa pb5 vdda pb8 pb7 pb4 pb2 pb3 32 31 30 29 28 27 26 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 pb1 pb0 pa15 pa14 pa9_ boot xtalin af0 (default) af0 (default) af0 (default) vdd vss nrst x32kin x32kout rtcout p33 vdd 33v vdd 33v vdd 33v vdd 33v p15 33v ap ap ht32f52331/ht32f52341 33 qfn-a 25 cldo af0 (default) p33 33v 33v 33v 33v swclk swdio pa12 pa13 pb10 pb11 pb12 pb13 af1 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 17 xtalout pb14 33v 33 vss 1 2 3 4 5 6 7 8 pa0 pa1 pa2 pa3 pa4 pa5 usbdm usbdp 33v 33v 33v 33v 33v 33v usb usb 3.3 v digital & analog io pad p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital i/o pad vdd vdd domain pad usb usb phy pad figure 8. ht32f52331/52341 33-pin qfn pin assignment rev. 1.51 27 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment pin assignment vssa pb6 vdda pb8 pb7 pc3 pc2 pc1 pb5 pb4 pb2 pb3 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 35 34 33 32 31 30 29 28 27 26 25 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc4 usbdm usbdp vss_2 vdd_2 pb1 pb0 pa15 pa14 pa10 pa9_ boot pa8 xtalin af0 (default) af0 (default) af0 (default) vdd_1 vss_1 nrst pb9 x32kin x32kout rtcout pc0 xtalout pb15 p33 vdd 33v vdd 33v vdd 33v vdd 33v vdd 33v p15 usb usb 33v 33v 33v 33v 33v 33v 33v ap ap p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad ht32f52331/ht32f52341 48 lqfp-a 37 12 24 36 cldo af0 (default) 33v pc5 p33 33v 33v p33 p33 33v 33v 33v usb usb phy pad swclk swdio vdd vdd domain pad pa12 pa13 pb10 pb11 pb12 pb13 pb14 af1 af1 pa11 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v figure 9. ht32f52331/52341 48-pin lqfp pin assignment rev. 1.51 28 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment table 3. ht32f52231/52241 series pin assignment for 24/28ssop, 33qfn, 48lqfp package package ht32f52231/52241 alternate function mapping af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 48 lqfp 33 qfn 28 ssop 24 ssop system default gpio adc n/a gptm /mctm spi usart /uart i 2 c n/a n/a n/a n/a n/a sctm n/a system other 1 1 4 4 pa0 adc_in2 gt_ch0 spi1_sck usr_rts i2c1_scl 2 2 5 5 pa1 adc_in3 gt_ch1 spi1_mosi usr_cts i2c1_sda 3 3 6 6 pa2 adc_in4 gt_ch2 spi1_miso usr_tx 4 4 7 7 pa3 adc_in5 gt_ch3 spi1_sel usr_rx 5 5 8 8 pa4 adc_in6 gt_ch0 spi0_sck ur1_tx i2c0_scl 6 6 9 9 pa5 adc_in7 gt_ch1 spi0_mosi ur1_rx i2c0_sda 7 7 10 pa6 adc_in8 gt_ch2 spi0_miso 8 8 11 pa7 adc_in9 gt_ch3 spi0_sel 9 pc4 adc_in10 usr_tx sctm0 10 pc5 adc_in11 usr_rx sctm1 11 pc6 mt_ch2 ur0_tx i2c0_scl 12 pc7 mt_ch2n ur0_rx i2c0_sda 13 9 12 10 cldo 14 10 13 11 vdd_1 15 11 14 12 vss_1 16 12 15 13 nrst 17 pb9 mt_ch3 18 13 x32kin pb10 gt_ch0 spi1_sel usr_tx sctm2 19 14 x32kout pb11 gt_ch1 spi1_sck usr_rx sctm3 20 15 16 14 rtcout pb12 spi0_miso ur0_rx sctm0 wakeup 21 16 17 15 xtalin pb13 ur0_tx i2c0_scl 22 17 18 16 xtalout pb14 ur0_rx i2c0_sda 23 pb15 mt_ch0 spi0_sel i2c1_scl 24 pc0 mt_ch0n spi0_sck i2c1_sda sctm3 25 pa8 usr_tx sctm2 26 18 19 17 pa9_ boot spi0_mosi sctm3 ckout 27 pa10 mt_ch1 spi0_mosi usr_rx 28 pa11 mt_ch1n spi0_miso sctm0 29 19 20 18 swclk pa12 30 20 21 19 swdio pa13 31 21 22 pa14 mt_ch0 spi1_sel usr_rts i2c1_scl 32 22 23 pa15 mt_ch0n spi1_sck usr_cts i2c1_sda sctm1 33 23 24 20 pb0 mt_ch1 spi1_mosi usr_tx i2c0_scl 34 24 25 21 pb1 mt_ch1n spi1_miso usr_rx i2c0_sda sctm2 35 vdd_2 36 33 vss_2 37 25 26 22 pb2 mt_ch2 spi0_sel ur1_tx 38 26 27 23 pb3 mt_ch2n spi0_sck ur1_rx sctm1 39 27 28 24 pb4 mt_brk spi0_mosi ur1_tx sctm0 40 28 pb5 gt_ch2 spi0_miso ur1_rx 41 pc1 mt_ch0 spi1_sel ur1_tx 42 pc2 mt_ch0n spi1_sck 43 pc3 mt_brk spi1_mosi ur1_rx 44 pb6 gt_ch3 spi1_miso ur0_tx 45 29 1 1 pb7 adc_in0 mt_ch1 spi0_miso ur0_tx i2c1_scl 46 30 2 2 pb8 adc_in1 mt_ch1n spi0_sel ur0_rx i2c1_sda 47 31 3 3 vdda 48 32 vssa note: the pin number 33 of the 33-pin qfn package is located at the bottom metal of the qfn package. rev. 1.51 29 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment pin assignment table 4. ht32f52331/52341 series pin assignment for 33qfn, 48lqfp package package ht32f52331/52341 alternate function mapping af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 48 lqfp 33 qfn system default gpio adc n/a gptm /mctm spi usart /uart i2c sci n/a n/a n/a n/a sctm n/a system other 1 1 pa0 adc_in2 gt_ch0 spi1_sck usr_rts i2c1_scl sci_clk 2 2 pa1 adc_in3 gt_ch1 spi1_mosi usr_cts i2c1_sda sci_dio 3 3 pa2 adc_in4 gt_ch2 spi1_miso usr_tx 4 4 pa3 adc_in5 gt_ch3 spi1_sel usr_rx 5 5 pa4 adc_in6 gt_ch0 spi0_sck ur1_tx i2c0_scl sci_clk 6 6 pa5 adc_in7 gt_ch1 spi0_mosi ur1_rx i2c0_sda sci_dio 7 pa6 adc_in8 gt_ch2 spi0_miso sci_det 8 pa7 adc_in9 gt_ch3 spi0_sel 9 pc4 adc_in10 usr_tx sctm0 10 pc5 adc_in11 usr_rx sctm1 11 7 usbdm 12 8 usbdp 13 9 cldo 14 10 vdd_1 15 11 vss_1 16 12 nrst 17 pb9 mt_ch3 18 13 x32kin pb10 gt_ch0 spi1_sel usr_tx sctm2 19 14 x32kout pb11 gt_ch1 spi1_sck usr_rx sctm3 20 15 rtcout pb12 spi0_miso ur0_rx sctm0 wakeup 21 16 xtalin pb13 ur0_tx i2c0_scl 22 17 xtalout pb14 ur0_rx i2c0_sda 23 pb15 mt_ch0 spi0_sel i2c1_scl 24 pc0 mt_ch0n spi0_sck i2c1_sda sctm3 25 pa8 usr_tx sci_clk sctm2 26 18 pa9_boot spi0_mosi sci_dio sctm3 ckout 27 pa10 mt_ch1 spi0_mosi usr_rx sci_det 28 pa11 mt_ch1n spi0_miso sci_det sctm0 29 19 swclk pa12 30 20 swdio pa13 31 21 pa14 mt_ch0 spi1_sel usr_rts i2c1_scl sci_clk 32 22 pa15 mt_ch0n spi1_sck usr_cts i2c1_sda sci_dio sctm1 33 23 pb0 mt_ch1 spi1_mosi usr_tx i2c0_scl 34 24 pb1 mt_ch1n spi1_miso usr_rx i2c0_sda sctm2 35 vdd_2 36 33 vss_2 37 25 pb2 mt_ch2 spi0_sel ur1_tx 38 26 pb3 mt_ch2n spi0_sck ur1_rx sctm1 39 27 pb4 mt_brk spi0_mosi ur1_tx sctm0 40 28 pb5 gt_ch2 spi0_miso ur1_rx 41 pc1 mt_ch0 spi1_sel ur1_tx 42 pc2 mt_ch0n spi1_sck 43 pc3 mt_brk spi1_mosi ur1_rx 44 pb6 gt_ch3 spi1_miso ur0_tx sci_clk 45 29 pb7 adc_in0 mt_ch1 spi0_miso ur0_tx i2c1_scl sci_det 46 30 pb8 adc_in1 mt_ch1n spi0_sel ur0_rx i2c1_sda sci_dio 47 31 vdda 48 32 vssa note: the pin number 33 of the 33-pin qfn package is located at the bottom metal of the qfn package. rev. 1.51 30 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment table 5. ht32f52231/52241 pin description pin number pin name type (note1) io structure (note2) output driving description 48lqfp 33qfn 28ssop 24ssop default function (af0) 1 1 4 4 pa0 ai/o 33v 4/8/12/16 ma pa0 2 2 5 5 pa1 ai/o 33v 4/8/12/16 ma pa1 3 3 6 6 pa2 ai/o 33v 4/8/12/16 ma pa2 4 4 7 7 pa3 ai/o 33v 4/8/12/16 ma pa3 5 5 8 8 pa4 ai/o 33v 4/8/12/16 ma pa4 6 6 9 9 pa5 ai/o 33v 4/8/12/16 ma pa5 7 10 pa6 ai/o 33v 4/8/12/16 ma pa6 8 11 pa7 ai/o 33v 4/8/12/16 ma pa7 9 pc4 ai/o 33v 4/8/12/16 ma pc4 10 pc5 ai/o 33v 4/8/12/16 ma pc5 11 7 pc6 ai/o pc6 12 8 pc7 ai/o pc7 13 9 12 10 cldo p core power ldo 1.5 v output it is recommended to connect a 1 f capacitor as close as possible between this pin and vss_1. 14 10 13 11 vdd_1 p voltage for digital i/o 15 11 14 12 vss_1 p ground reference for digital i/o 16 12 15 13 nrst note 3 i 33v_pu external reset pin and external wakeup pin in the power- down mode 17 pb9 note 3 i/o (v dd ) 33v 4/8/12/16 ma pb9 18 13 pb10 note 3 ai/o (v dd ) 33v 4/8/12/16 ma x32kin 19 14 pb11 note 3 ai/o (v dd ) 33v 4/8/12/16 ma x32kout 20 15 16 14 pb12 note 3 i/o (v dd ) 33v 4/8/12/16 ma rtcout 21 16 17 15 pb13 ai/o 33v 4/8/12/16 ma xtalin 22 17 18 16 pb14 ai/o 33v 4/8/12/16 ma xtalout 23 pb15 i/o 33v 4/8/12/16 ma pb15 24 pc0 i/o 33v 4/8/12/16 ma pc0 25 pa8 i/o 33v 4/8/12/16 ma pa8 26 18 19 17 pa9 i/o 33v_pu 4/8/12/16 ma pa9_boot 27 pa10 i/o 33v 4/8/12/16 ma pa10 28 pa11 i/o 33v 4/8/12/16 ma pa11 29 19 20 18 pa12 i/o 33v_pu 4/8/12/16 ma swclk 30 20 21 19 pa13 i/o 33v_pu 4/8/12/16 ma swdio 31 21 22 pa14 i/o 33v 4/8/12/16 ma pa14 32 22 23 pa15 i/o 33v 4/8/12/16 ma pa15 33 23 24 20 pb0 i/o 33v 4/8/12/16 ma pb0 34 24 25 21 pb1 i/o 33v 4/8/12/16 ma pb1 35 vdd_2 p voltage for digital i/o 36 33 vss_2 p ground reference for digital i/o 37 25 26 22 pb2 i/o 33v 4/8/12/16 ma pb2 38 26 27 23 pb3 i/o 33v 4/8/12/16 ma pb3 39 27 28 24 pb4 i/o 33v 4/8/12/16 ma pb4 40 28 pb5 i/o 33v 4/8/12/16 ma pb5 41 pc1 i/o 33v 4/8/12/16 ma pc1 42 pc2 i/o 33v 4/8/12/16 ma pc2 43 pc3 i/o 33v 4/8/12/16 ma pc3 44 pb6 i/o 33v 4/8/12/16 ma pb6 45 29 1 1 pb7 ai/o 33v 4/8/12/16 ma pb7 46 30 2 2 pb8 ai/o 33v 4/8/12/16 ma pb8 47 31 3 3 vdda p analog voltage for adc and comparator 48 32 vssa p ground reference for the adc and comparator note: 1. i = input, o = output, a = analog port, p = power supply, pu = pull-up, v dd = v dd power 2. 33v = 3.3v tolerant. 3. these pins are located at the v dd power domain. rev. 1.51 31 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 pin assignment pin assignment table 6. ht32f52331/52341 pin description pin number pin name type (note1) io structure (note2) output driving description 48lqfp 33qfn default function (af0) 1 1 pa0 ai/o 33v 4/8/12/16 ma pa0 2 2 pa1 ai/o 33v 4/8/12/16 ma pa1 3 3 pa2 ai/o 33v 4/8/12/16 ma pa2 4 4 pa3 ai/o 33v 4/8/12/16 ma pa3 5 5 pa4 ai/o 33v 4/8/12/16 ma pa4 6 6 pa5 ai/o 33v 4/8/12/16 ma pa5 7 pa6 ai/o 33v 4/8/12/16 ma pa6 8 pa7 ai/o 33v 4/8/12/16 ma pa7 9 pc4 ai/o 33v 4/8/12/16 ma pc4 10 pc5 ai/o 33v 4/8/12/16 ma pc5 11 7 usbdm ai/o usb differential data bus conforming to the universal serial bus standard. 12 8 usbdp ai/o usb differential data bus conforming to the universal serial bus standard. 13 9 cldo p core power ldo 1.5 v output it is recommended to connect a 1 f capacitor as close as possible between this pin and vss_1. 14 10 vdd_1 p voltage for digital i/o 15 11 vss_1 p ground reference for digital i/o 16 12 nrst note 3 i 33v_pu -- external reset pin and external wakeup pin in the power-down mode 17 pb9 note 3 i/o (v dd ) 33v 4/8/12/16 ma pb9 18 13 pb10 note 3 ai/o (v dd ) 33v 4/8/12/16 ma x32kin 19 14 pb11 note 3 ai/o (v dd ) 33v 4/8/12/16 ma x32kout 20 15 pb12 note 3 i/o (v dd ) 33v 4/8/12/16 ma rtcout 21 16 pb13 ai/o 33v 4/8/12/16 ma xtalin 22 17 pb14 ai/o 33v 4/8/12/16 ma xtalout 23 pb15 i/o 33v 4/8/12/16 ma pb15 24 pc0 i/o 33v 4/8/12/16 ma pc0 25 pa8 i/o 33v 4/8/12/16 ma pa8 26 18 pa9 i/o 33v_pu 4/8/12/16 ma pa9_boot 27 pa10 i/o 33v 4/8/12/16 ma pa10 28 pa11 i/o 33v 4/8/12/16 ma pa11 29 19 pa12 i/o 33v_pu 4/8/12/16 ma swclk 30 20 pa13 i/o 33v_pu 4/8/12/16 ma swdio 31 21 pa14 i/o 33v 4/8/12/16 ma pa14 32 22 pa15 i/o 33v 4/8/12/16 ma pa15 33 23 pb0 i/o 33v 4/8/12/16 ma pb0 34 24 pb1 i/o 33v 4/8/12/16 ma pb1 35 vdd_2 p voltage for digital i/o 36 33 vss_2 p ground reference for digital i/o 37 25 pb2 i/o 33v 4/8/12/16 ma pb2 38 26 pb3 i/o 33v 4/8/12/16 ma pb3 39 27 pb4 i/o 33v 4/8/12/16 ma pb4 40 28 pb5 i/o 33v 4/8/12/16 ma pb5 41 pc1 i/o 33v 4/8/12/16 ma pc1 42 pc2 i/o 33v 4/8/12/16 ma pc2 43 pc3 i/o 33v 4/8/12/16 ma pc3 44 pb6 i/o 33v 4/8/12/16 ma pb6 45 29 pb7 ai/o 33v 4/8/12/16 ma pb7 46 30 pb8 ai/o 33v 4/8/12/16 ma pb8 47 31 vdda p analog voltage for adc and comparator 48 32 vssa p ground reference for the adc and comparator note: 1. i = input, o = output, a = analog port, p = power supply, pu = pull-up, v dd = v dd power 2. 33v = 3.3v tolerant. 3. these pins are located at the v dd power domain. rev. 1.51 32 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics 5 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. s tresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min max unit v dd external main supply voltage v ss - 0.3 v ss + 3.6 v v dda external analog supply voltage v ssa - 0.3 v ssa + 3.6 v v in input voltage on i/o v ss - 0.3 v ss + 0.3 v t a ambient operating temperature range -40 +85 c t stg storage temperature range -55 +150 c t j maximum junction temperature +125 c p d total power dissipation 500 mw v esd electrostatic discharge voltage - human body mode -4000 +4000 v recommended dc operating conditions table 8. recommended dc operating conditions t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd i/o o perating voltage 2.0 3.3 3.6 v v dda analog operating voltage 2.5 3.3 3.6 v on-chip ldo voltage regulator characteristics table 9. ldo characteristics t a = 25c, unless otherwise specif ed. symbol parameter conditions min typ max unit v ldo internal regulator output voltage v dd 2.0v regulator input @ i ldo = 35ma and voltage vari - ant = 5%, after trimming. 1.425 1.5 1.57 v i ldo output current v dd = 2.0v regulator input @ v ldo = 1.5v 30 35 ma c ldo external filter capacitor value for internal core power supply the capacitor value is depen - dent on the core power cur - rent consumption 1 f rev. 1.51 33 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics power consumption table 10. ht32f52231/52241 power consumption characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd supply current (run mode) v dd = 3.3v, hse = 8mhz, pll = 40mhz, f hclk = 40mhz, f pclk = 48mhz, all peripherals enabled 12 ma v dd = 3.3v, hse = 8mhz, pll = 40mhz, f hclk = 40mhz, f pclk = 40mhz, all peripherals disabled 7 ma v dd = 3.3v, hse off, pll off, lsi on, f hclk = 32khz, f pclk = 32khz, all peripherals enabled 45 a v dd = 3.3v, hse off, pll off, lsi on, f hclk = 32khz, f pclk = 32khz, all peripherals disabled 40 a supply current (sleep mode) v dd = 3.3v, hse = 8mhz, pll = 40mhz, f hclk = 0mhz, f pclk = 40mhz, all peripherals enabled 7.5 ma v dd = 3.3v, hse = 8mhz, pll = 40mhz, f hclk = 0mhz, f pclk = 40mhz, all peripherals disabled 2 ma supply current (deep-sleep1 mode) v dd = 3.3v, all clock off (hse/pll/f hclk ), ldo in low power mode, lsi on, rtc on 35 a supply current (deep-sleep2 mode) v dd = 3.3v, all clock off (hse/pll/f hclk ), ldo off dmos on, lsi on, rtc on 5 a supply current (power-down mode) v dd = 3.3v, ldo off, dmos off, lse on, lsi on, rtc on a v dd = 3.3v, ldo off, dmos off, lse off, lsi on, rtc off 1.5 a rev. 1.51 34 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics table 11. ht32f52331/52341 power consumption characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd supply current (run mode) v dd = 3.3v, hse = 8mhz, pll = 48mhz, f hclk = 48mhz, f pclk = 48mhz, all peripherals enabled 16 ma v dd = 3.3v, hse = 8mhz, pll = 48mhz, f hclk = 48mhz, f pclk = 48mhz, all peripherals disabled 8.5 ma v dd = 3.3v, hse off, pll off, lsi on, f hclk = 32khz, f pclk = 32khz, all peripherals enabled 45 a v dd = 3.3v, hse off, pll off, lsi on, f hclk = 32khz, f pclk = 32khz, all peripherals disabled 40 a supply current (sleep mode) v dd = 3.3v, hse = 8mhz, pll = 48mhz, f hclk = 0mhz, f pclk = 48mhz, all peripherals enabled 10 ma v dd = 3.3v, hse = 8mhz, pll = 48mhz, f hclk = 0mhz, f pclk = 48mhz, all peripherals disabled 2.5 ma supply current (deep-sleep1 mode) v dd = 3.3v, all clock off (hse/pll/f hclk ), ldo in low power mode, lsi on, rtc on 35 a supply current (deep-sleep2 mode) v dd = 3.3v, all clock off (hse/pll/f hclk ), ldo off dmos on, lsi on, rtc on 5 a supply current (power-down mode) v dd = 3.3v, ldo off, dmos off, lse on, lsi on, rtc on a v dd = 3.3v, ldo off, dmos off, lse off, lsi on, rtc off 1.5 a note: 1. hse means high speed external oscillator. hsi means 8mhz high speed internal oscillator. 2. lse means 32.768khz low speed external oscillator. lsi means 32khz low speed internal oscillator. 3. rtc means real time clock. 4. code = while (1) { 208 nop } executed in flash. rev. 1.51 35 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics reset and supply monitor characteristics table 12. v dd power reset characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v por power on reset threshold (rising voltage on v dd ) t a = -40c~ +85c 1.66 1.79 1.90 v v pdr power down reset threshold (falling voltage on v dd ) 1.49 1.64 1.78 v v porhyst por hysteresis 150 mv t por reset delay time v dd = 3.3v 0.1 0.2 ms note: 1. data based on characterization results only, not tested in production. 2. guaranteed by design, not tested in production. 3. if the ldo is turned on, the vdd por has to be in the de-assertion condition. when the vdd por is in the assertion state then the ldo will be turned off. table 13. lvd/bod characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod voltage of brown out detection t a = -40c ~ 85c after factory-trimmed (v dd falling edge) 2.02 2.1 2.18 v v lvd voltage of low voltage detection t a = -40c ~ 85c (v dd falling edge) lvds = 000 2.17 2.25 2.33 v lvds = 001 2.32 2.4 2.48 v lvds = 010 2.47 2.55 2.63 v lvds = 011 2.62 2.7 2.78 v lvds = 100 2.77 2.85 2.93 v lvds = 101 2.92 3.0 3.08 v lvds = 110 3.07 3.15 3.23 v lvds = 111 3.22 3.3 3.38 v v lvdhtst lvd hysteresis v dd = 3.3v 100 mv t sulvd lvd setup time v dd = 3.3v 5 s t atlvd lvd active delay time v dd = 3.3v s i ddlvd operation current note3 v dd = 3.3v 5 15 a note: 1. data based on characterization results only, not tested in production. 2. guaranteed by design, not tested in production. 3. bandgap current is not included. 4. lvds feld is in the pwrcu lvdcsr register rev. 1.51 36 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics external clock characteristics table 14. high speed external clock (hse) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd operation range 2.0 3.6 v f hse high speed external oscillator frequency (hse) 4 16 mhz c lhse load capacitance v dd = 3.3v, r esr = 100 @ 16mhz 22 pf r fhse internal feedback resistor between xtalin and xtalout pins 1 m r esr equivalent series resistance* v dd = 3.3v, c l = 12pf @ 16mhz, hsedr = 0 160 v dd = 2.4v, c l = 12pf @ 16mhz, hsedr = 1 d hse hse oscillator duty cycle 40 60 % i ddhse hse oscillator current consumption v dd = 3.3v @ 16mhz tbd ma i pwdhse hse oscillator power down current v dd = 3.3v 0.01 a t suhse hse oscillator s tartup time v dd = 3.3v 4 ms table 15. low speed external clock (lse) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd operation range 2.0 3.6 v f ck_lse lse frequency v bak = 2.0v ~ 3.6v 32.768 khz r f internal feedback resistor 10 m? r esr equivalent series resistance v bak = 3.3v 30 tbd k? c l recommended load capacitances v bak = 3.3v 6 tbd pf i ddlse oscillator supply current (high current mode) f ck_lse = 32.768khz, r esr = 50k?, c l >= 7pf v bak = 2.0v ~ 2.7v t a = -40c ~ +85c 3.3 6.3 a oscillator supply current (low current mode) f ck_lse = 32.768khz, r esr = 50k?, c l < 7pf v bak = 2.0v ~ 3.6v t a = -40c ~ +85c 1.8 3.3 a power down current 0.01 a t sulse startup time ( low current mode) f ck_lsi = 32.768khz, v bak = 2.0v ~ 3.6v 500 ms note: the following guidelines are recommended to increase the stability of the crystal circuit of the hse / lse clock in the pcb layout: the crystal oscillator should be located as close as possible to the mcu to keep the trace length s as short as possible to reduce any parasitic capacitance. shield lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise. keep any high frequency signal lines away from the crystal area to prevent any crosstalk adverse effects . rev. 1.51 37 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics internal clock characteristics table 16. high speed internal clock (hsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd operation range 2.0 3.6 v f hsi hsi frequency v dd = 3.3v @ 25c 8 mhz acc hsi factory calibrated hsi oscilla- hsi oscilla- tor f requency accuracy v dd = 3.3v, t a = 25c -2 2 % v dd = 2.5v ~ 3.6v, t a = -40c ~ +85c -3 3 % v dd = 2.0v ~ 3.6v t a = -40c ~ +85c -4 4 % duty duty cycle f hsi = 8mhz 35 65 % i ddhsi oscillator supply current f hsi = 8mhz 300 500 a power down current 0.05 a t suhsi startup time f hsi = 8mhz 10 s table 17. low speed internal clock (lsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed internal oscillator frequency (lsi) v dd = 3.3v, t a = -40c ~ +85c 21 32 43 khz acc lsi lsi frequency accuracy after factory-trimmed, v dd = 3.3v, t a = 25c -10 +10 % i ddlsi lsi oscillator operating current v dd = 3.3v, t a = 25c 0.4 0.8 a t sulsi lsi oscillator s tartup time v dd = 3.3v, t a = 25c 100 s pll characteristics table 18. pll characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll input clock 4 16 mhz f ck_pll pll output clock 16 48 mhz t lock pll lock time 200 s memory characteristics table 19. flash memory characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu number of guaranteed program/erase cycles before failure. (endurance) t a = -40c ~ +85c 10 k cycles t ret data retention time t a = -40c ~ +85c 10 years t prog word programming time t a = -40c ~ +85c 20 s t erase page erase time t a = -40c ~ +85c 2 ms t merase mass erase time t a = -40c ~ +85c 10 ms rev. 1.51 38 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics i/o port characteristics table 20. i/o port characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low level input current 3.3v io v i = v ss , on-chip pull-up resister disabled. 3 a reset pin 3 a i ih high level input current 3.3v io v i = v dd, on-chip pull-down resister disabled. 3 a reset pin 3 a v il low level input voltage 3.3v io - 0.5 v dd 0.35 v reset pin - 0.5 v dd 0.35 v v ih high level input voltage 3.3v io v dd 0.65 v dd + 0.5 v reset pin v dd 0.65 v dd + 0.5 v v hys schmitt trigger input voltage hysteresis 3.3v io v dd 0.12 mv reset pin v dd 0.12 mv i ol low level output current (gpio sink current) 3.3v io 4ma drive, v ol = 0.4v 4 ma 3.3v io 8ma drive, v ol = 0.4v 8 ma 3.3v io 12ma drive, v ol = 0.4v 12 ma 3.3v io 16ma drive, v ol = 0.4v 16 ma i oh high level output current (gpio source current) 3.3v i/o 4ma drive, v oh = v dd - 0.4v 4 ma 3.3v i/o 8ma drive, v oh = v dd - 0.4v 8 ma 3.3v i/o 12ma drive, v oh = v dd - 0.4v 12 ma 3.3v i/o 16ma drive, v oh = v dd - 0.4v 16 ma v ol low level output voltage 3.3v 4ma drive io, i ol = 4ma 0.4 v 3.3v 8ma drive io, i ol = 8ma 0.4 v 3.3v 12ma drive io, i ol = 12ma 0.4 v 3.3v 16ma drive io, i ol = 16ma 0.4 v v oh high level output voltage 3.3v 4ma drive io, i oh = 4ma v dd - 0.4 v 3.3v 8ma drive io, i oh = 8ma v dd - 0.4 v 3.3v 12ma drive io, i ol = 12ma v dd - 0.4 v 3.3v 16ma drive io, i ol = 16ma v dd - 0.4 v r pu internal pull-up resistor 3.3v i/o 46 k r pd internal pull-down resistor 3.3v i/o 46 k rev. 1.51 39 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics adc characteristics table 21. adc characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda operating voltage 2.5 3.3 3.6 v v adcin a/d converter input voltage range 0 v ref+ v v ref+ a/d converter reference voltage v dda v dda v i adc current consumption v dda = 3.3v 1 tbd ma i adc_dn power down current consumption v dda = 3.3v 0.1 a f adc a/d converter clock 0.7 16 mhz f s sampling rate 0.05 1 mhz t dl data latency 12.5 1/f adc cycles t s&h sampling & hold time 3.5 1/f adc cycles t adcconv a/d converter conversion time 16 1/f adc cycles r i input sampling switch resistance 1 k c i input sampling capacitance no pin/pad capacitance included 16 pf t su startup up time 1 s n resolution 12 bits inl integral non-linearity error f s = 750khz, v dda = 3.3v 2 5 lsb dnl differential non-linearity error f s = 750khz, v dda = 3.3v 1 lsb e o offset error 10 lsb e g gain error 10 lsb note: 1. guaranteed by design, not tested in production. 2. the fgure below shows the equivalent circuit of the a/d converter sample-and-hold input stage where c i is the storage capacitor, r i is the resistance of the sampling switch and r s is the output impedance of the signal source v s . normally the sampling phase duration is approximately, 3.5/f adc . the capacitance, c i , must be charged within this time frame and it must be ensured that the voltage at its terminals becomes suffciently close to v s for accu- racy. to guarantee this, r s is not allowed to have an arbitrarily large value. rev. 1.51 40 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics sar adc c i sample r i r s v s figure 10. adc sampling network model the worst case occurs when the extremities of the input range (0v and v ref ) are sampled consecutively. in this situation a sampling error below ? lsb is ensured by using the following equation: i 2n i adc s r )2 ln( cf 5.3 r ? ? ? where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where the a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, r s may be larger than the value indicated by the equation above. sctm/gptm/mctm characteristics table 22. sctm/gptm/mctm characteristics symbol parameter conditions min typ max unit f tm timer clock source for gptm and mctm 48 mhz t res timer resolution time 1 f tm f ext external single frequency on channel 1 ~ 4 1/2 f tm res timer resolution 16 bits rev. 1.51 41 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics i 2 c characteristics table 23. i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min max min max min max f scl scl clock frequency 100 400 1000 khz t scl(h) scl clock high time 4.5 1.125 0.45 s t scl(l) scl clock low time 4.5 1.125 0.45 s t fall scl and sda fall time 1.3 0.34 0.135 s t rise scl and sda rise time 1.3 0.34 0.135 s t su(sda) sda data setup time 500 125 50 ns t h(sda) sda data hold time 0 0 0 ns t su(sta) start condition setup time 500 125 50 ns t h(sta) start condition hold time 0 0 0 ns t su(sto) stop condition setup time 500 125 50 ns note: 1. guaranteed by design, not tested in production. 2. to achieve 100 khz standard mode, the peripheral clock frequency must be higher than 2mhz. 3. to achieve 400 khz fast mode, the peripheral clock frequency must be higher than 8mhz. 4. to achieve 1mhz fast mode plus, the peripheral clock frequency must be higher than 20mhz. 5. the above characteristic parameters of the i 2 c bus timing are based on : seq_filter = 01 and comb_filter_en is disabled. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 11. i 2 c timing diagrams rev. 1.51 42 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics spi characteristics table 24. spi characteristics symbol parameter conditions min typ max unit spi master mode f sck (1/t sck ) spi master output sck clock frequency master mode, spi peripheral clock frequency f pclk f pclk /2 mhz t sck(h) t sck(l) sck clock high and low time t sck /2 -2 t sck /2 +1 ns t v(mo) data output valid time 5 ns t h(mo) data output hold time 2 ns t su(mi) data input setup time 5 ns t h(mi) data input hold time 5 ns spi slave mode f sck (1/t sck ) spi master output sck clock frequency slave mode, spi peripheral clock frequency f pclk f pclk /3 mhz duty sck spi slave input sck clock duty cycle 30 70 % t su(sel) sel enable setup time 3 t pclk ns t h(sel) sel enable hold time 2 t pclk ns t a(so) data output access time 3 t pclk ns t dis(so) data output disable time 10 ns t v(so) data output valid time 25 ns t h(so) data output hold time 15 ns t su(si) data input setup time 5 ns t h(si) data input hold time 4 ns note: t sck = 1/f sck ; t pclk = 1/f pclk . spi output (input) clock frequency f sck ; spi peripheral clock frequency f pclk . sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi ) t su(mi ) t v(mo) t h(mo) t su(mi ) t h(mi ) data valid data valid data valid data valid figure 12. spi timing diagrams C spi master mode rev. 1.51 43 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 13. spi timing diagrams C spi slave mode with cpha=1 rev. 1.51 44 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics usb characteristics the usb interface is usb-if certifed C full speed. table 25. usb dc electrical characteristics symbol parameter conditions min typ max unit v dd usb operating voltage 3.0 3.6 v v di differential input sensitivity | usbdp - usbdm | 0.2 v v cm common mode voltage range 0.8 2.5 v v se single-ended receiver threshold 0.8 2.0 v v ol pad output low voltage r l of 1.5k to v dd33 0 0.3 v v oh pad output high voltage 2.8 3.6 v v crs differential output signal cross-point voltage 1.3 2.0 v z drv driver output resistance 10 c in transceiver pad capacitance 20 pf note: 1. guaranteed by design, not tested in production. 2. the usb functionality is ensured down to 2.7v but for not the full usb electrical characteris - tics which will experience degradation in the 2.7v to 3.0v v dd voltage range. 3. rl is the load connected to the usb driver usbdp. t r t f 90% 90% 10% 10% fall time rise time v crs figure 14. usb signal rise time and fall time and cross-point voltage (vcrs) defnition table 26. usb ac electrical characteristics symbol parameter conditions min typ max unit t r rise time c l = 50pf 4 20 ns t f fall time c l = 50pf 4 20 ns t r/f rise time / fall time matching t r/f = t r / t f 90 110 % rev. 1.51 45 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 electrical characteristics package information 6 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information rev. 1.51 46 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 package information 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.341 bsc d 0.069 e 0.025 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.200 0.300 c 8.660 bsc d 1.750 e 0.635 bsc f 0.100 0.250 g 0.410 1.270 h 0.100 0.250 0 8 rev. 1.51 47 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 package information package information 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.390 bsc d 0.069 e 0.025 bsc f 0.004 0.0098 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.200 0.300 c 9.900 bsc d 1.750 e 0.635 bsc f 0.100 0.250 g 0.410 1.270 h 0.100 0.250 0 8 rev. 1.51 48 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 package information saw type 33-pin (4mm4mm) qfn outline dimensions 33 symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.006 0.008 0.010 d 0.157 bsc e 0.157 bsc e 0.016 bsc d2 0.104 0.106 0.108 e2 0.104 0.106 0.108 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.700 0.750 0.800 a1 0.000 0.020 0.050 a3 0.203 bsc b 0.150 0.200 0.250 d 4.000 bsc e 4.000 bsc e 0.400 bsc d2 2.650 2.700 2.750 e2 2.650 2.700 2.750 l 0.350 0.400 0.450 k 0.200 rev. 1.51 49 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 package information package information 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.276 bsc c 0.354 bsc d 0.276 bsc e 0.020 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.063 i 0.002 0.006 j 0.018 0.024 0.030 k 0.004 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 9.000 bsc b 7.000 bsc c 9.000 bsc d 7.000 bsc e 0.500 bsc f 0.170 0.220 0.270 g 1.350 1.400 1.450 h 1.600 i 0.050 0.150 j 0.450 0.600 0.750 k 0.090 0.200 0 D 7 rev. 1.51 50 of 50 april 11, 2017 32-bit arm ? cortex?-m0+ mcu ht32f52231/HT32F52241/ht32f52331/ht32f52341 package information copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw/en/home. |
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